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SAA8122A
Digital Still Camera Processor (ImagIC family)
Rev. 01 -- 20 April 2000 Objective specification
1. Description
The DSC SAA8122A is a high performance, low power, single-chip Million Instructions Per Second (MIPS) based signal processor, part of the ImagIC family, which is dedicated to image processing, compression, formatting and storage. The DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022, 2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy implementation of a complete system solution and fast development of high performance consumer digital still cameras. The SAA8122A is designed as a single-chip device, able to perform all treatments and connections required for a wide range of Digital Still Cameras. Its embedded RISC CPU, for which the development environment is available, enables shorter development and validation cycles, as well as faster feature upgrade. Since one of the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a DSP (with advanced embedded algorithm) for camera signal processing is integrated with a high level of programmability for pulses generation. The JPEG core is hardware based in order to allow high-speed image data compression.
2. Features
c
c
2.1 General
s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA), with RGB Bayer filters up to 2 Mpixels s Performs an advanced RGB to YUV conversion s Includes a smart measurement unit to speed up the control loop (focus, auto white balance, etc.) s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text insertion features s Includes an embedded JPEG encoder/decoder unit s Includes a MIPS PR3001 CPU, running at a frequency in a range from 12 to 28 MHz s PRISC compatible PI-bus architecture, interrupt, power management, clock and reset architectures s Includes a dedicated video bus supporting SDRAM memory for picture storage
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
s Interface to ROM, DRAM, SRAM, flash and PC Card [Compact Flash and SSFDC (SmartMedia)] s Integrated general purpose peripheral units like a UART, timers, an I2C-bus transceiver, ADC converters, RTC and I/O ports s Includes USB and RS-232C communication interfaces.
2.2 External interfaces
s Two UART (RS-232) data ports with DMA capabilities (187.5 kbit/s) including hardware flow control RxD, TxD, RTS, CTS for modem support s 32 general purpose, bidirectional I/O interface pins, the first 8 bits may also be used as interrupt inputs s Two PWM outputs (8-bit resolution).
2.3 CPU related features
s s s s s s s s 32-bit PR3001 core 1-kbyte data cache and 4-kbyte instruction cache Programmable low-power mode, including wake-up on interrupt Memory management unit [Translation Lookaside Buffer (TLB)] Two built in 24-bit general purpose timers and one 24-bit watchdog timer Real-time clock unit (active in sleep mode) On-chip 8-kbyte SRAM for storing code which needs fast execution Platform software based on real-time pSOS (plug-in Silicon Operating System).
2.4 DSP features
s Advanced colour reconstruction s Programmable digital filters for noise reduction and contour enhancement s 16 programmable measurement windows allowing to perform the measurements necessary for exposure, white balance and focus adjustment in a DSC system; available measurement outputs for exposure, white balance and focus control.
2.5 Pulse pattern generator features
s Programmable through dedicated PC-software, allowing to drive all CCDs currently present in the market, as well as CDS/AGC/ADC chips: up to 8 x 8 kpixels.
2.6 JPEG
s Fully ISO10918 compliant s Supports Tiff, Exif 2.1, DCF & DPOF s Quick compression (4 images/s for a 1.3 Mpixels resolution).
2.7 USB interface
s Fully compatible with USB.
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Objective specification
Rev. 01 -- 20 April 2000
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
2.8 Card interfaces
s Compatible with all SSFDC/CF cards on the market.
2.9 Bus
s Bus structure allows for parallel processing depending on software implementation, allowing easy system optimization.
2.10 SDRAM interface features
s Supports up to 128 Mbyte of SDRAM and 16-bit wide addressses s Bus speed: 1 or 2 times CCD pixel clock s 32-bit bus width.
3. Quick reference data
Table 1: Symbol VDDD VDDA IP VI Quick reference data Parameter digital supply voltage analog supply current total supply current input voltage general 5 V tolerant cells only VO Tamb fclk
[1] [2] [3]
[3]
Conditions
[1] [2]
Min 3 3 - 0 0 0 0 -
Typ 3.3 3.3 360 - - - 25 25
Max 3.6 3.6 560 VDDD 5.5 VDDD 70 27
Unit V V mA V V V C MHz
fclk = 25 MHz
output voltage ambient temperature clock frequency
output active
The supplies considered as digital supply (VDDD) are: VDDD, VDDD(RTC). The supplies considered as analog supply (VDDA) are: VDDA(SPLL), VDDA(PLL), VDDA(BG), VDDA(PPG1), VDDA(ADC), VDDA(OUTPUT1), VDDA(OUTPUT2), VDDA(LCDR), VDDA(LCDG), VDDA(LCDB), VDDA(DLL). Including voltage on outputs in 3-state mode; only valid when supply voltage is present.
4. Ordering information
Table 2: Ordering information Package Name SAA8122AEL LFBGA324 Description plastic low profile fine-pitch ball grid array package; 324 balls; body 16 x 16 x 1.2 mm Version SOT571-1 Type number
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Objective specification
Rev. 01 -- 20 April 2000
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(c) Philips Electronics N.V. 2000. All rights reserved. 9397 750 07048
5. Block diagram
Philips Semiconductors
TCB PC-CARD CONTROLLER DRAM MEMORY CONTROLLER STATIC MEMORY CONTROLLER PERIPHERAL CONTROLLER
INTERUPT CONTROLLER
USB
UART
JPEG CODEC
EBIU
PR3001 CPU
INTERUPT CONTROLLER
PLL CCD
PI BCU
SAA8122A
SLAVE GROUP INTERFACE
Digital Still Camera Processor (ImagIC family)
VDO BCU
CAMDSP
8K SRAM I2 C TRANSCIEVER POWER MANAGEMENT CONTROLLER ANALOG DIGITAL CONTROLLER
TIMER
TIMER
TIMER
GPIO +INT
FOUR GPIO
RTC
FCE686
SAA8122A
4 of 26
Fig 1. Block diagram.
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
handbook, full pagewidth
to LCD
to TV
lens CCD FXA1022 10 TDA9952 to cards (SSFDC, CF)
SAA8122A
V-DRIVER TDA9991
USB IRDA to PC
FCE687
Fig 2. System block diagram.
6. Pinning information
6.1 Pinning
handbook, halfpage V U T R P N M L K J H G F E D C B A
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
FCE677
SAA8122AEL
Fig 3. Pin configuration (bottom view).
6.2 Pin description
Table 3: Symbol VDDD VSSA(DLL) VDDA(DLL) DISP_VSYNC IO1/IRQ17 VDDA(LCDG) VDDA(OUTPUT2)
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Pin description Pin A1 A2 A3 A4 A5 A6 A7 Type O I/O P P Description digital supply voltage analog ground for DLL of PPG analog supply voltage for DLL of PPG digital vertical synchronization signal I/O port 0 bit 1 or interrupt request 17 analog supply voltage for DAC component G analog supply voltage for DAC video output 2
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Objective specification
Rev. 01 -- 20 April 2000
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol
Pin description...continued Pin A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Type P I P I I I O I I P O I/O I/O O O O I I P P I O I P I/O P P P I/O I/O O O P P I I P Description band-gap 1 ground for BG of video DAC system reset input/output; active LOW ground for RTC timer 0 capture input 0 timer 2 count pulse input timer 1 count pulse input timer 0 PWM output analog input signal 0 for level measurement analog input signal 3 for level measurement ground for ADC PPG analog signal 1 I/O port 0 bit 6 or interrupt request 22 I/O port 0 bit 3 or interrupt request 19 analog green signal video output signal 2 analog reference ground test clock input for surround scan chains test clock input oscillator input from a specific CCD crystal analog supply voltage for SPLL ground for PLL timer 0 count pulse input analog reference ground for ADC analog input signal 2 for level measurement analog supply voltage for ADC I/O port 2 bit 7 analog supply voltage for PPG analog supply voltage for PPG analog supply voltage for DLL of PPG I/O port 0 bit 7 or interrupt request 23 I/O port 0 bit 4 or interrupt request 20 analog red signal analog blue signal analog supply voltage for DAC video output 1 analog supply voltage for BG of video DAC test mode select input oscillator input from a 32 kHz crystal oscillator input from a 10 MHz crystal timer 2 gate input analog supply voltage for PLL
(c) Philips Electronics N.V. 2000. All rights reserved.
CREF_BG1 VSS(BG) SYSRSTIN VSS(RTC) T0_CAP0 CNT2 CNT1 PWM0 ADC0 ADC3 VSS(ADC) ANPPG1 IO6/IRQ22 IO3/IRQ19 LCD_G VIDEO_OUT2 VSSA(ref) SC_TCK TCK XTALCCDIN VDDA(SPLL) VSS(PLL) CNT0 VSSA(ref)(ADC) ADC2 VDDA(ADC) IO23 VDDA(PPG1) VDDA(PPG0) VDDA(DLL) IO7/IRQ23 IO4/IRQ20 LCD_R LCD_B VDDA(OUTPUT1) VDDA(BG) TMS XTAL32KIN XTAL10IN GATE2 VDDA(PLL)
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol PWM1 ADC1 IO22 IO16 ANPPG7
Pin description...continued Pin C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E14 E15 E16 E17 E18 F1 F2 Type O I I/O I/O O P O I/O I/O P P O I I I O I/O I/O I/O O O O P I/O P P O O I P I I/O I/O I/O I O O Description timer 1 PWM output analog input signal 1 for level measurement I/O port 2 bit 6 I/O port 2 bit 0 PPG analog signal 7 analog ground for PPG digital horizontal synchronization signal I/O port 0 bit 5 or interrupt request 21 I/O port 0 bit 0 or interrupt request 16 analog ground for display RGB ground for DAC video output band-gap 2 test data output test data input oscillator output from a 32 kHz crystal oscillator output from a 10 MHz crystal timer 0 capture input 1 timer 0 gate input timer 2 PWM output I/O port 2 bit 1 I/O port 1 bit 7 I/O port 1 bit 3 PPG digital signal 0 PPG digital signal 1 PPG analog signal 8 analog supply voltage for PPG I/O port 0 bit 2 or interrupt request 18 analog supply voltage for DAC component R analog supply voltage for DAC component B video output signal 1 system reset output; active LOW test reset input digital supply voltage for RTC oscillator output from a specific CCD crystal timer 1 gate input I/O port 2 bit 2 I/O port 1 bit 2 I/O port 1 bit 1 UART external clock PPG digital signal 4 PPG digital signal 5
(c) Philips Electronics N.V. 2000. All rights reserved.
VSSA(PPG1) DISP_HSYNC IO5/IRQ21 IO0/IRQ16 VSSA(LCD) VSS(OUTPUT) CREF_BG2 TDO TDI XTAL32KOUT XTAL10OUT T0_CAP1 GATE0 PWM2 IO17 IO15 IO11 PPG1 PPG2 ANPPG8 VDDA(PPG0) IO2/IRQ18 VDDA(LCDR) VDDA(LCDB) VIDEO_OUT1 SYSRST TRST VDDD(RTC) XTALCCDOUT GATE1 IO18 IO10 IO9 UA_CLK PPG5 PPG6
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol PPG3 ANPPG5 ANPPG3 VSS VSS VDD VDD VDD VDD VDD IO20 IO19 IO12 CTS RXD TXD PPG10 PPG12 PPG8 PPG4 ANPPG6 ANPPG2 VDD VSS VSS VSS VSS VDD IO21 IO13 RTS SDA SCL n.c. HDHREF VDVS PPG13 PPG7 PPG14 ANPPG4 VDD
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Pin description...continued Pin F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 H6 H7 Type O O O I/O I/O I/O I I O O O O O O O I/O I/O O I/O I/O I/O I/O O O O O Description PPG digital signal 2 PPG analog signal 5 PPG analog signal 3 ground ground supply voltage supply voltage supply voltage supply voltage supply voltage I/O port 2 bit 4 I/O port 2 bit 3 I/O port 1 bit 4 UART clear to send UART receive input UART transmit output PPG digital signal 17 PPG digital control signal 1 PPG digital signal 8 PPG digital signal 3 PPG analog signal 6 PPG analog signal 2 supply voltage ground ground ground ground supply voltage I/O port 2 bit 5 I/O port 1 bit 5 UART request to send I2C-bus data I2C-bus clock not connected PPG horizontal synchronization signal PPG vertical synchronization signal PPG digital control signal 2 PPG digital control signal 6 PPG digital control signal 3 PPG analog signal 4 supply voltage
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Rev. 01 -- 20 April 2000
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol VSS VSS VSS VSS VDD IO14 RXVPI n.c. RXVMI TXVPO RXDATA CCD_IM2 CCD_IM3 CCD_IM4 PPG11 PPG9 VDD VDD VSS VSS VSS VSS VDD IO8
Pin description...continued Pin H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 Type I/O I I/O O I I I I O O I/O O O I/O I/O I/O I I I I I Description ground ground ground ground supply voltage I/O port 1 bit 6 USB not connected USB USB USB digital image signal 2 digital image signal 3 digital image signal 4 PPG digital signal 18 PPG digital signal 8 supply voltage supply voltage ground ground ground ground supply voltage I/O port 1 bit 0 USB USB EBIU D2 EBIU D3 EBIU D0 digital image signal 10 digital image signal 9 digital image signal 8 digital image signal 1 digital image signal 0 supply voltage supply voltage ground ground ground ground supply voltage
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SUSPEND TXOE D2 D3 D0 CCD_IM10 CCD_IM9 CCD_IM8 CCD_IM1 CCD_IM0 VDD VDD VSS VSS VSS VSS VDD
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol TXVMO D1 D4 D6 D7 D8 SD_A[0] SD_A[3] SD_A[2] CCD_IM6 CCD_IM7 CCD_IM5 VDD VSS VSS VSS VSS VDD D5 D9 D11 D14 D13 D12 SD_A[7] SD_A[8] SD_A[9] SD_A[4] SD_A[1]
Pin description...continued Pin K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 Type O I/O I/O I/O I/O I/O O O O I I I I/O I/O I/O I/O I/O I/O O O O O O I I/O O I/O I O Description USB EBIU D1 EBIU D4 EBIU D6 EBIU D7 EBIU D8 SDRAM controller address bus bit 0 SDRAM controller address bus bit 3 SDRAM controller address bus bit 2 digital image signal 6 digital image signal 7 digital image signal 5 supply voltage ground ground ground ground supply voltage EBIU D5 EBIU D9 EBIU D11 EBIU D14 EBIU D13 EBIU D12 SDRAM controller address bus bit 7 SDRAM controller address bus bit 8 SDRAM controller address bus bit 9 SDRAM controller address bus bit 4 SDRAM controller address bus bit 1 digital image signal 11 supply voltage ground ground ground ground supply voltage EBIU D10 EBIU controller SE signal for SSFDC card; active LOW EBIU D15 EBIU controller WAIT signal for PC card 2; active LOW EBIU controller CE signal for SSFDC card; active LOW
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CCD_IM11 VDD VSS VSS VSS VSS VDD D10 SC_SE D15 PC_WAIT2 SC_CE
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol SC_CLE SD_A[12] SD_A[13] SD_A[14] SD_A[10] SD_A[6] SD_A[5] VDD VDD VDD VDD VDD SC_ALE PC2_CE1 PC2_CE2 PC_REG
Pin description...continued Pin M18 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 Type O O O O O O O O O O O O O O O I O O O I/O I/O I/O I/O I/O I/O O I/O O O O O O O Description EBIU controller CLE signal for SSFDC card SDRAM controller address bus bit 12 SDRAM controller address bus bit 13 SDRAM controller address bus bit 14 SDRAM controller address bus bit 10 SDRAM controller address bus bit 6 SDRAM controller address bus bit 5 supply voltage supply voltage supply voltage supply voltage supply voltage EBIU controller ALE signal for SSFDC card EBIU controller CE1 signal for PC card 2; active LOW EBIU controller CE2 signal for PC card 2; active LOW EBIU controller REG signal for PC cards; active LOW EBIU controller WAIT signal for PC card 1; active LOW EBIU controller IORD signal for PC cards; active LOW EBIU controller IORD signal for PC cards; active LOW SDRAM controller clock output SDRAM controller clock input SDRAM controller chip select for memory 2; active LOW SDRAM controller clock enable SDRAM controller address bus bit 11 supply voltage SDRAM controller data bus bit 7 I/O port 3 bit 1 I/O port 4 bit 6 EBIU A25 (Strapin[0] during boot sequence) EBIU A21 (Strapin[4] during boot sequence) supply voltage EBIU A14 EBIU controller clock signal for external peripherals EBIU A9 EBIU controller CAS signal for DRAM memory for lower byte; used as data strobe signal for lower byte for general chip select; active LOW EBIU controller CE1 signal for PC card 1; active LOW EBIU controller CE2 signal for PC card 1; active LOW SDRAM controller chip select for memory 0; active LOW SDRAM controller chip select for memory 1; active LOW SDRAM controller chip select for memory 3; active LOW
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PC_WAIT1 IOWR_WE IORD_RE SD_CLKOUT SD_CLKIN SD_CS2 SD_CLKEN SD_A[11] VDD SD_D[7] IO25 IO38 A25 A21 VDD A14 SCLK A9 CAS0 PC1_CE1 PC1_CE2 SD_CS0 SD_CS1 SD_CS3
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol SD_D[4] SD_RAS SD_D[6] SD_D[13] IO30 IO37 A24 A19 A18 A13 A5 CS6 CAS1 OE RAS SD_CAS SD_WE SD_D[3] SD_D[8] SD_D[10] SD_D[14] IO26 IO29 IO33 IO36 A23 A16 A12 A3 CS7 CS4 WE CS_WAIT
Pin description...continued Pin R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 Type I/O O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I/O I/O I/O I/O I/O Description SDRAM controller data bus bit 4 SDRAM controller row address strobe; active LOW SDRAM controller data bus bit 6 SDRAM controller data bus bit 13 I/O port 3 bit 6 I/O port 4 bit 5 EBIU A24 (Strapin[1] during boot sequence) EBIU A19 (Strapin[6] and Strapin[9] during boot sequence) EBIU A18 (Strapin[10] during boot sequence) EBIU A13 EBIU A5 EBIU controller chip select 6; active LOW EBIU controller CAS signal for DRAM memory for upper byte; used as data strobe signal for upper byte for general chip select; active LOW EBIU controller output enable signal; active LOW EBIU controller RAS signal for DRAM memory; active LOW SDRAM controller column address strobe; active LOW SDRAM controller write enable; active LOW SDRAM controller data bus bit 3 SDRAM controller data bus bit 8 SDRAM controller data bus bit 10 SDRAM controller data bus bit 14 I/O port 3 bit 2 I/O port 3 bit 5 I/O port 4 bit 1 I/O port 4 bit 4 EBIU A23 (Strapin[2] during boot sequence) EBIU A16 EBIU A12 EBIU A3 EBIU controller chip select 7; active LOW EBIU controller chip select 4; active LOW EBIU controller write enable signal; active LOW EBIU controller wait signal for chip selects; active LOW SDRAM controller DQ mask enable for byte 0; active LOW SDRAM controller DQ mask enable for byte 1; active LOW SDRAM controller data bus bit 2 SDRAM controller data bus bit 9 SDRAM controller data bus bit 11 SDRAM controller data bus bit 15 I/O port 3 bit 3
(c) Philips Electronics N.V. 2000. All rights reserved.
SD_DQM0 SD_DQM1 SD_D[2] SD_D[9] SD_D[11] SD_D[15] IO27
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 3: Symbol IO32 IO34 A22 A17 A11 A8 A4 A2 CS5 CS3 CS0 SD_D[0] SD_D[1] SD_D[5] SD_D[12] IO24 IO28 IO31 IO35 IO39 A20 A15 A10 A7 A6 A1 A0 CS2 CS1
Pin description...continued Pin U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Type I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O Description I/O port 4 bit 0 I/O port 4 bit 2 EBIU A22 (Strapin[3] during boot sequence) EBIU A17 (Strapin[11] during boot sequence) EBIU A11 EBIU A8 EBIU A4 EBIU A2 EBIU controller chip select 5; active LOW EBIU controller chip select 3; active LOW EBIU controller chip select 0; active LOW SDRAM controller data bus bit 0 SDRAM controller data bus bit 1 SDRAM controller data bus bit 5 SDRAM controller data bus bit 12 I/O port 3 bit 0 I/O port 3 bit 4 I/O port 3 bit 7 I/O port 4 bit 3 I/O port 4 bit 7 EBIU A20 (Strapin[5] and Strapin[8] during boot sequence) EBIU A15 EBIU A10 EBIU A7 EBIU A6 EBIU A1 EBIU A0 EBIU controller chip select 2; active LOW EBIU controller chip select 1; active LOW
9397 750 07048
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
7. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDD VDDA VI Parameter digital supply voltage analog supply voltage DC input voltage general 5 V tolerant cells only IDD ISS Tstg
[1] [2] [3] [4] [5]
[1] [2] [2] [3] [4]
Conditions
Min -0.5 -0.5 -0.5 -0.5 - - 0
Max 4 4
Unit V V
VDD + 0.5 V -0.5 60 60 125 V mA mA C
DC supply current per supply pin DC ground current per ground pin storage temperature
[4]
[5]
Value may not exceed 4 V. Including voltage on outputs in 3-state mode. Only valid when supply voltage is present. The peak current is limited to 10 times the corresponding maximum current. Dependent of package and not yet determined.
8. Characteristics
Table 5: Symbol VDDD VDDA(DLL) VDDA(LCDR) VDDA(LCDG) VDDA(LCDB) General supply characteristics Parameter digital supply voltage analog supply voltage for DLL analog supply voltage for LCDR output of DAC analog supply voltage for LCDG output of DAC analog supply voltage for LCDB Conditions Min 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
[1]
Typ 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
Max 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Unit V V V V V V V V V V V V V V
VDDA(OUTPUT1) analog supply voltage for video output 1 of DAC VDDA(OUTPUT2) analog supply voltage for video output 2 of DAC VDDA(ADC) VDDA(PPG1) VDDA(PPG0) VDDA(BG) VDDA(PLL) VDDA(SPLL) VDDD(RTC)
[1]
analog supply voltage for ADC analog supply voltage for PPG analog supply voltage for PPG analog supply voltage for bandgap analog supply voltage for PLL analog supply voltage for SPLL digital supply voltage for RTC
3.0
VDDD(RTC) is the single supply which may be on when the others are off. In this case the I/Os of the SAA8122A have to be at 0 V.
9397 750 07048
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Rev. 01 -- 20 April 2000
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Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Table 6: Symbol
Operating characteristics Parameter analog supply voltage for LCDR output of DAC analog supply voltage for LCDG output of DAC analog supply voltage for LCDB output of DAC Conditions Min 3.0 3.0 3.0 3.0 3.0 3.0 (4) code 0 code 511 1.18 3.0 8 0 8-bit 0 3.0 Typ 3.3 3.3 3.3 3.3 3.3 3.3 1.22 0.225 1.625 1 8 75 5 9 1 8 1 9 3.3 2 3.3 Max 3.6 3.6 3.6 3.6 3.6 3.6 1.26 5 100 5 5 3.6 0.2 10 3.3 100 3.6 Unit V V V V V V V V V k pF bit pF bit k pF bit k pF bit V V bit pF V kHz V
VDDA(LCDR) VDDA(LCDG) VDDA(LCDB)
VDDA(OUTPUT1) analog supply voltage for video output 1 of DAC VDDA(OUTPUT2) analog supply voltage for video output 2 of DAC VDDA(BG) VBG VOL VOH RL CL RES RL CL RES RL CL RES RL CL RES ADC VDDA(ADC) VDD RES Ci Vi fsample PLL VDDA(PLL) analog supply voltage for analog PLL analog supply voltage for analog ADC supply voltage difference between VDDA and VDDA(ADC) resolution input capacitance input voltage sample frequency analog supply voltage for bandgap bandgap reference voltage LOW-level output voltage HIGH-level output voltage load resistance load capacitance resolution load resistance load capacitance resolution load resistance load capacitance resolution load resistance load capacitance resolution
LCD channels (1 k buffer)
LCD channels (75 mode)
VIDEO_OUT channels (1 k buffer)
VIDEO_OUT channels (1 k mode)
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Table 6: Symbol VDD fclk SPLL VDDA(SPLL) VDD
Operating characteristics...continued Parameter supply voltage difference between VDDA and VDDA(PLL) clock frequency analog supply voltage for analog SPLL supply voltage difference between VDDA and VDDA(SPLL) trip level of power-on reset time that VDDA has to be above 2.65 V before internal reset signal is asserted time that VDDA has to be above 2.65 V before internal reset signal is de-asserted analog supply voltage for analog DLL Conditions Min 3.0 Typ 96 3.3 Max 0.2 3.6 0.2 Unit V MHz V V
Power-on reset Vtrip tHIGH 1.5 2.07 2.65 2 V s
tLOW
-
-
8
s
Analog PPG VDDA(DLL) 3.0 3.0 3.3 3.3 3.6 0.2 3.6 0.2 V V V V
VDD-DDA(DLL) supply voltage difference between VDDA and VDDA(DLL) VDDA(PPG1); VDDA(PPG0) analog supply voltage for analog PPG
VDD-DDA(PPG) supply voltage difference between VDDA and VDDA(PPG1) or VDDA(PPG0) I/Os (VDDD = VDDA, Tamb = 0 to 60 C) Data and control inputs
SD_CLKIN
VIL VIH Ci IIL IIH Ilu(I/O) LOW-level digital input voltage HIGH-level digital input voltage input capacitance LOW-level input current HIGH-level input current I/O latch-up current VI = 0 V VI = VDDD -0.5 < VDDD + 0.5 0 0.7VDDD 100 1.14 0.3VDDD VDDD 1 1 V V pF A A mA
CS_WAIT, PC_WAIT1, PC_WAIT2, SC_TCK, TCK, TDI, TMS, TRST, CCD_IM0 to CCD_IM11, CNT0 to CNT2, GATE0 to GATE2, T0_CAP0, T0_CAP1, CTS, RXD, UA_CLK, RXDATA, RXVMI, RXVPI
VIL VIH Ci IIL IIH Ilu(I/O) LOW-level digital input voltage HIGH-level digital input voltage input capacitance LOW-level input current HIGH-level input current I/O latch-up current LOW-level digital input voltage VI = 0 V VI = VDDD -0.5 < VDDD < 5.5 0 2.0 100 0 1.2 0.8 5.5 1 1 0.8 V V pF A A mA V
SYSRSTIN
VIL
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Table 6: Symbol VIH Vhys Ci IIL IIH Ilu(I/O)
Operating characteristics...continued Parameter HIGH-level digital input voltage hysteresis voltage input capacitance LOW-level input current HIGH-level input current I/O latch-up current VI = 0 V VI = VDDD -0.5 < VDDD < 5.5 Conditions Min 2.0 0.4 100 Typ 1.2 Max 5.5 1 1 Unit V V pF A A mA
Data and control outputs
ANPPG1 to ANPPG8
VOL VOH Co(L)(max) IOL IOH LOW-level digital output voltage HIGH-level digital output voltage maximum output load capacitance LOW-level output current HIGH-level output current VOL = 0.4 V; VOH = VDDA - 0.4 VOH = VDDA - 0.4 IOL = 4 mA IOH = 4 mA
[1]
0 4 -4
-
0.4 VDDA 100 -
V V pF mA mA
VDDA - 0.4 -
SCLK, SD_A[0] to SD_A[14], SD_CAS, SD_CLKEN, SD_CLKOUT, SD_CS0 to SD_CS3, SD_DQM0 to SD_DQM1, SD_RAS, SD_WE
VOL VOH Ci Co(L)(max) IOL IOH IOZ LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current IOL = 4 mA IOH = -4 mA VOL = 0.4 V VOH = VDDD - 0.4 VO = 0; VO = VDDD IOL = 2 mA IOH = -2 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4 VO = 0; VO = VDD
[1] [1]
0 VDDD - 0.4 -4 -
1 -
0.4 VDDD 100 1
V V pF pF A mA A
TDO, SYSRST, PWM0 to PWM2, RTS, TXD, SUSPEND, TXOE, TXVMO, TXVPO, DISP_HSYNC, DISP_VSYNC
VOL VOH Ci Co(L)(max) IOL IOH IOZ LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current 0 2 -2 2.2 0.4 VDDD 30 1 V V pF pF mA mA A VDDD - 0.4 -
CAS0, CAS1, CS0 to CS7, IORD_RE, IOWR_WE, OE, PC_REG, PC1_CE1, PC1_CE2, RAS, SC_ALE, SC_SE, WE, PPG1 to PPG14
VOL VOH Ci Co(L)(max) IOL IOH
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LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current
IOL = 4 mA IOH = -4 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4
[1]
0 4 -4
2.4 -
0.4 VDDD 30 -
V V pF pF mA mA
VDDD - 0.4 -
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Table 6: Symbol IOZ
Operating characteristics...continued Parameter 3-state output leakage current Conditions VO = 0; VO = VDDD Min Typ Max 1 Unit A
Data and control I/Os
SD_D[0] to SD_D[15]
VIL VIH VOL VOH Ci Co(L)(max) IOL IOH IOZ IIL IIH VIL VIH VOL VOH Ci Co(L)(max) IOL IOH IOZ IIL IIH VIL VIH VOL VOH Ci Co(L)(max) IOL IOH LOW-level digital input voltage HIGH-level digital input voltage LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current LOW-level input current HIGH-level input current LOW-level digital input voltage HIGH-level digital input voltage LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current LOW-level input current HIGH-level input current LOW-level digital input voltage HIGH-level digital input voltage LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current IOL = 4 mA IOH = -4 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4 VO = 0; VO = VDDD VI = 0 VI = VDDD IOL = 4 mA IOH = -4 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4 VO = 0; VO = VDDD VI = 0 VI = VDDD IOL = 2 mA IOH = -2 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4
[1] [1]
0 0.7VDDD 0 4 -4 0 0.7VDDD 0 4 -4 0 0.7VDDD 0 2 -2
1.2 2.5 2.3 -
0.3VDDD VDDD 0.4 VDDD 100 1 1 1 0.6VDDD VDDD 0.4 VDDD 30 1 1 1 0.3VDDD VDDD 0.4 30 -
V V V V pF pF mA mA A A A V V V V pF pF mA mA A A A V V V V pF pF mA mA
VDDD - 0.4 -
A0 to A15, IO8 to IO15, HDHREF, VDVS
VDDD - 0.4 -
IO16 to IO23, IO0/IRQ16, IO1/IRQ17, IO2/IRQ18, IO3/IRQ19, IO4/IRQ20, IO5/IRQ21, IO6/IRQ22, IO7/IRQ23
VDDD - 0.4 -
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Table 6: Symbol IOZ IIL IIH
Operating characteristics...continued Parameter 3-state output leakage current LOW-level input current HIGH-level input current LOW-level digital input voltage HIGH-level digital input voltage LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current LOW-level input current HIGH-level input current LOW-level digital input voltage HIGH-level digital input voltage LOW-level digital output voltage HIGH-level digital output voltage input capacitance maximum output load capacitance LOW-level output current HIGH-level output current 3-state output leakage current LOW-level input current HIGH-level input current I/Os LOW-level digital input voltage HIGH-level digital input voltage hysteresis voltage LOW-level digital output voltage input capacitance maximum output load capacitance IOL = 3 mA [1]
Conditions VO = 0; VO = VDDD VI = 0 VI = VDDD IOL = 2 mA IOH = -2 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4 VO = 0; VO = VDDD VI = 0 VI = VDDD IOL = 1 mA IOH = -1 mA VOL = 0.4 V; VOH = VDDD - 0.4 VOH = VDDD - 0.4 VO = 0; VO = VDDD VI = 0 VI = VDDD
Min 0 2.0 2 -2 0 2.0 0 1 -1 -
Typ 1.5 1.4 -
Max 1 1 1 0.8 5.5 0.4 VDDD 30 1 1 1 0.8 5.5 0.4 VDDD 30 1 1 1
Unit A A A V V V V pF pF mA mA A A A V V V V pF pF mA mA A A A
IO4 to IO31
VIL VIH VOL VOH Ci Co(L)(max) IOL IOH IOZ IIL IIH
VDDD - 0.4 -
IO32 to IO39
VIL VIH VOL VOH Ci Co(L)(max) IOL IOH IOZ IIL IIH I2C-bus VIL VIH Vhys VOL Ci Co(L)(max)
VDDD - 0.4 -
SCL and SDA
0 0 3.2 0.3VDDD 0.3VDDD 0.4 400 V V V V pF pF
0.005VDDD -
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Table 6: Symbol IOZ IIL IIH
[1]
Operating characteristics...continued Parameter 3-state output leakage LOW-level input current HIGH-level input current Conditions VO = 0; VO = VDDD VI = 0 VI = VDDD Min Typ Max 1 1 1 Unit A A A
The maximum capacitance value given does not take into account the signal frequency. For critical signals the maximum capacitance has to be weighted according to the signal frequency and external devices constraints.
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9. Package outline
LFBGA324: plastic low profile fine-pitch ball grid array package; 324 balls; body 16 x 16 x 1.2 mm SOT571-1
D
B
A
ball A1 index area
E
A
A2 A1 detail X
C D1 e
V U T R P N M L K J H G F E D C B A 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
b
vMB
w M
y1 C vMA
y
e
E1
X
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.70 A1 0.45 0.35 A2 1.35 1.05 b 0.55 0.45 D 16.1 15.9 D1 13.6 E 16.1 15.9 E1 13.6 e 0.8 v 0.15 w 0.1 y 0.12 y1 0.10
OUTLINE VERSION SOT571-1
REFERENCES IEC JEDEC MO-205 EIAJ
EUROPEAN PROJECTION
ISSUE DATE 00-01-20
Fig 4. SOT571-1.
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10. Soldering
10.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
10.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C.
10.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
10.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
10.5 Package related soldering information
Table 7: Package BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC [3], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [2] Reflow [1] suitable suitable suitable suitable suitable
suitable not recommended [3] [4] not recommended [5]
[2]
[3] [4] [5]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
11. Revision history
Table 8: 01 Revision history CPCN Description Objective specification; initial version
Rev Date 20000420
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12. Data sheet status
Datasheet status Objective specification Preliminary specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Product specification
Production
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
13. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
15. Licenses
Purchase of Philips I2C components
14. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Internet: http://www.semiconductors.philips.com
(SCA69)
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Contents
1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 External interfaces . . . . . . . . . . . . . . . . . . . . . . 2 CPU related features . . . . . . . . . . . . . . . . . . . . 2 DSP features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pulse pattern generator features . . . . . . . . . . . 2 JPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Card interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 3 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SDRAM interface features . . . . . . . . . . . . . . . . 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23 Package related soldering information . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
(c) Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 April 2000 Document order number: 9397 750 07048

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